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[交流] Convert Allegro to PADs

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发表于 2016-12-22 12:33:32 | 显示全部楼层 |阅读模式
Prepare the Allegro design(s) for migration, as follows:
- Copy all data in the dictionary C:\MentorGraphics\9.4PADS\SDD_HOME\translators\skill_scripts into $HOME\pcbenv folder.
- Open the design file and in the Allegro command prompt window enter these command lines:
     Command> skill load “dfl_main” (include quotes)
     Command> main out
- Then, the Allegro to Wxpedition Translator box is appeared, click "Start One Way"
- When the SKILL script has completed, if any errors were found, fix them and rerun the SKILL script. The migration will not complete correctly if all errors      are not fixed.

2.Allegro to PADs maspping table.
From Allegro Element -> To PADS Element
Assy_Line -> Not Supported
Board Outline -> Board Outline object
Break Outs -> Traces & Vias (Fanouts)
Component_Body Outline_1 -> User layer (Component Body Outline_1)
Component_Body Outline_2 -> User layer (Component Body Outline_2)
DAM -> Not Supported
Dielectric -> Not Supported
Dimension_Keepout -> Not Supported
Drill -> Not Supported
Error -> Not Supported
Fixture_Outline -> Not Supported
Force -> Not Supported
Glue_Mask_1 -> Not Supported
Glue_Mask_2 -> Not Supported
Head_Insertion -> Not Supported
Insertion_Machine_Keepout -> User layer (Insertion)
Milling -> Not Supported
One-Way_Region -> User layer (One Way Region)
Panel_Outline -> Not Supported
Paste_Mask_1 -> Paste Mask Top
Paste_Mask_2 -> Paste Mask Bottom
Place_1 -> Layer 20 (Placement Outline)
Place_2 -> Layer 20 (Placement Outline)
Placement_Keepout_1 -> User layer
Placement_Keepout_2 -> User layer

Placement_Region_1 -> User layer
Placement_Region_2 -> User layer
Power Plane -> Layer
Prepreg -> Not Supported
Probe_1 and Probe_2 -> Not Supported
Probe_Area -> Not Supported
Probe_Symbol N-> ot Supported
Routing_Keepout -> Keepout  (Trace & Via)
Shape_Edit -> Not Supported
Sheet_Dielectric -> Not Supported
Signal_X -> Layer (Signal)
Silkscreen_1 -> Silkscreen Outline Top
Silkscreen_2 -> Silkscreen Outline Bottom
Solder_Paste_1 -> Paste Mask Top
Solder_Paste_2 -> Paste Mask Bottom
Soldermask_1 -> Soldermask Top
Soldermask_2 -> Soldermask Bottom
Test Points -> Test Points
TestPoint_Keepout -> Not Supported
TestPoint_Outline -> Not Supported
TestPoint_Reference -> Not Supported
Thermal -> Supported
Trace Keepout -> Keepout (Trace)
User Defined Layer -> User layer
Via Keepout -> Keepout (Via)
Aperture Table -> Not Supported
Artwork Format -> Not Supported
Artwork Simulation -> Not Supported
Artwork Stackup -> Not Supported

Drill Simulation -> Not Supported
Drill Table -> Not Supported
Mill Table -> Not Supported
Area Fills -> Copper Pour or Plane Area
Area Fills (Protected) -> Copper Pour or Plane Area
Area Fill Tie Bar and Cutouts -> Not Supported
Classic Area Fills -> Copper Pour or Plane Area
Cutouts -> Copper Keepout
Cutouts (Protected) -> Copper Keepout
No Connect Rules -> Not supported
Placement Outline -> Not Supported
Power Fill -> Plane Layer
Route Keepout -> Keepout (Trace)
Signal Layer -> Electrical Layer
Split Power Planes -> Plane Layer
Trace Keepout -> Keepout (Trace)
Via Keepout -> Keepout (Via)
Color map settings -> Not Supported
Component Ref. Des. (Top) -> Ref. Des. on Silkscreen Top
Component Ref. Des. (Bottom) -> Ref. Des. on Silkscreen Bottom
Dimensioning -> Not Supported
Drill Symbols -> Supported
Guides -> Not supported
Net Type Patterns -> Not Supported
Part Name -> Not Supported
Pin Ref. Des. -> Pin Numbers
Shapes on User Defined Layers -> Shapes on User Layers

Shapes on Route Layers -> Shapes on Routing Layers
Targets/Registration Marks -> Graphics on User Layers
Text on User Defined Layer -> Text on User Layer
Text on Route Layer -> Text (Keepout)
Blind Padstacks -> SMD Padstacks
Blind/Buried Vias -> Buried Vias
Blind/Buried Vias (Protected) -> Buried Vias

Break Outs (Protected) T-> races & Vias
Breakouts (Component) -> Traces
Buried Padstacks -> Only for 2 pin parts, maps to Buried Part
Component Type Rules -> Not Supported
Components -> Parts
Components (Fixed) -> Parts
Components (Protected) -> Parts
Drilled Holes -> Part Holes
Fixed Components -> Parts
Jumpers -> Parts
MicroVias -> Vias (small diameter)
MicroVias (Protected) -> Vias (small diameter)
Mounting Holes -> Additional pins in decal
No Cleanup Vias -> Vias
Pins (Protected) -> Parts
Reuse Block (Primitive) -> Treated as single component
Reuse Block (Replica linked) -> Components and traces
Reuse Block (Replica un-linked) -> Treated as editable components & traces
Reuse Block (Smashed linked) -> Components and traces
Reuse Block (Smashed un-linked) -> Treated as editable components & traces
Shield Trace -> Traces

Shield Trace (Protected) -> Traces
Teardrops -> Not Supported
Test Coupon -> Not Supported
Test Points -> Test Points
Through Padstacks -> Through Padstacks
Through Vias -> Through Vias
Through Vias (Protected) -> Through Vias
Traces -> Traces
Traces (Protected) -> Traces
Traces in Cell -> Not supported
Component to Component Rules -> Supported
Component Type Rules -> Not Supported
Highspeed Rules -> Not supported
Hybird Objects -> Not Supported
MCM Objects -> Not Supported
Net Types -> Net Classes
Pin Type, SLT -> Not Supported
RF Objects -> Not Supported
Thermal -> Not Supported
Variants -> Not Supported


 楼主| 发表于 2016-12-23 09:48:29 | 显示全部楼层

Function is convert the PCB layout design from Allegro program to PADs Mentor program.
When the client need PADs file, we convert Allegro to PADs. That's all.
发表于 2017-1-12 08:51:26 | 显示全部楼层
Thank you for your share!
发表于 2017-2-20 17:45:07 | 显示全部楼层
楼主,不会用啊
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